1. Field of the Invention
The present invention relates to a semiconductor device that fixes a potential on an input signal wiring, that is connected to either an input terminal or an input/output terminal, by a pull-up or a pull-down.
2. Description of Related Art
As the number of pins increases, semiconductor devices of the type described above do not retain an input signal wiring, that is connected to an input terminal or an input/output terminal, in a floating state, but fix it at a potential xe2x80x9cHxe2x80x9d by a pull-up or at a potential xe2x80x9cLxe2x80x9d by a pull-down. This is because, unless potentials on all input signal wirings are controlled immediately after the power is turned on, the potentials do not stabilize if the input signal wirings are in a floating state, and the control therefor is very complex when many pins are present.
Before shipping out semiconductor devices, a semiconductor manufacturer must conduct input leak tests to measure whether potentials on the input signal wirings, that are connected to input terminals or input/output terminals, leak to the power source voltage VDD side or to the ground voltage VSS side.
A proposed technology that enables the input leak test is described in Japanese Laid-open Patent Application HEI 4-213849. Prior art technology 1 described in the publication will be described below with reference to FIG. 7.
Referring to FIG. 7, a semiconductor device includes a test terminal 10 and a plurality of input terminals 20, 30. The test terminal 10 connects to a control circuit 12. The control circuits 12 has output wirings that define an inversion signal wiring 14 and a non-inversion signal wiring 16.
The input terminals 20 and 30 are connected through input signal wirings 22 and 32 to input circuits 24 and 34, respectively. The input signal wiring 22 is grounded through a pull-down MIS (metal-insulation-silicon) transistor, for example, a N-type MOS (metal-oxide-silicon) transistor 26. The transistor 26 has a gate that is connected to the inversion signal wiring 14. Power source voltage VDD is applied to the input signal wiring 32 through a pull-up MIS transistor, for example a P-type MOS transistor 36. The transistor 36 has a gate that is connected to the non-inversion signal wiring 16.
Therefore, during normal operation, when a signal at level xe2x80x9cLxe2x80x9d is applied to the test terminal 10, the inversion signal wiring 14 of the control circuit 12 attains logic level xe2x80x9cHxe2x80x9d, the N-type MOS transistor 26 turns on, and the input signal wiring 22 has a potential fixed at level xe2x80x9cLxe2x80x9d. On the other hand, the non-inversion signal wiring 16 of the control circuit 12 attains logic level xe2x80x9cLxe2x80x9d, the P-type MOS transistor 36 turns on, and the input signal wiring 32 has a potential fixed at level xe2x80x9cHxe2x80x9d.
During an input leak test, a signal at a potential level xe2x80x9cHxe2x80x9d is applied to the test terminal 10. As a result, the inversion signal wiring 14 of the control circuit 12 attains logic level xe2x80x9cLxe2x80x9d, the N-type MOS transistor 26 turns off, and the input signal wiring 22 is placed in a floating state. On the other hand, the non-inversion signal wiring 16 of the control circuit 12 attains logic level xe2x80x9cHxe2x80x9d, the P-type MOS transistor 36 turns off, and the input signal wiring 32 is also placed in a floating state. In this manner, when the input signal wirings 22 and 32 are placed in a floating state, the input leak test can be correctly conducted. If a current flows during the test, it is determined that the tested semiconductor device is defective.
FIG. 8 shows a semiconductor device in which the structure shown in FIG. 7 is applied. A test cell 40 shown in FIG. 8 corresponds to the test terminal 10 of FIG. 7.
As shown in FIG. 8, a total of n number of above-described input cells or input/output cells 50-1, 50-2, . . . 50-n having input terminals 20, 30 or input/output terminals are disposed in a peripheral circuit region extending along four edges of the semiconductor device. Accordingly, the inversion signal wirings 14 and the non-inversion signal wirings 16 connected to the test cells 40 need to be formed along generally the entire circumference of the peripheral circuit region of the semiconductor device.
However, the wiring capacitance of the inversion and non-inversion signal wirings 14 and 16 that extend such a long distance reaches several tens pF. Also, the gate capacitance of each of the pull-down or pull-up transistors 26, 36 is several tens fF. However, when a large number of these transistors are present, their total gate capacitance reaches several tens pF. As a consequence, the control circuit 12 shown in FIG. 7 needs to be composed of circuits having a large capacitance. Therefore, the control circuit 12 having the large capacitance occupies a large area. Moreover, the wiring capacitance of the inversion and non-inversion signal wirings 14, 16 and the total gate capacitance of the pull-down and pull-up transistors greatly depend on the size of a chip. Accordingly, the capacitance of the control circuit 12 is required to be determined depending on the size of a chip, which is inconvenient.
When the inversion and non-inversion signal wirings 14, 16 have a large wiring capacitance, problems of signal delays cannot be ignored. This is because, in recent years, the time for an input leak test is controlled in units of sub-seconds, and a higher operation speed is required.
Also, when the inversion and non-inversion signal wirings 14, 16 have a large wiring capacitance, the waveform of the control signal becomes blunt. This makes it difficult to design circuits to provide logic signals to turn on or turn off the gates of the pull-down or pull-up transistors 26, 36 that are located far from the control circuit 12.
The inventor of the present application proposed an improved technology in Japanese Laid-open patent application HEI 7-176618 to solve the above-described prior art problems.
FIG. 9 shows the technology disclosed the above-described publication. Referring to FIG. 9, a test cell 40 includes a test terminal 10, a control signal wiring 42 connected to the test terminal 10, an N-type MOS transistor 44 that always maintains the potential on the control signal wiring 42 at level xe2x80x9cLxe2x80x9d, and an inverter 46 provided in the control signal wiring 42. The control signal wiring 42 is formed along generally the entire circumference of the peripheral circuit region of the semiconductor device, as shown in FIG. 10.
FIG. 9 also shows two input cells 50-1 and 50-2 that have substantially the same structure of those shown in FIG. 7. Each of the two input cells 50-1 and 50-2 has a buffer 100 provided in the control signal wiring 42. Each of the buffer 100 is formed from two serially connected inverters 100-1 and 100-2.
The input cell 50-1 has a pull-down N-type MOS transistor 26. A control signal buffered by the buffer 100 is inputted in a gate of the N-type MOS transistor 26. On the other hand, the input cell 50-2 has a pull-up P-type MOS transistor 36. A signal between the two inverters 100-1 and 100-2 that compose the buffer 100 is supplied to a gate of the P-type MOS transistor 36.
By the structure described above, during normal operation when the potential of the test terminal 10 is at xe2x80x9cLxe2x80x9d level, both of the N-type and P-type MOS transistors 26 and 36 are turned on, and the potential on each of the input signal wirings 22 and 32 is fixed. During input leak test when the potential of the test terminal 10 is at xe2x80x9cHxe2x80x9d level, both of the N-type and P-type MOS transistors 26 and 36 are turned off, and each of the input signal wirings 22 and 32 is set in a floating state.
As shown in FIG. 10, the peripheral circuit region of the semiconductor device is also provided with a variety of cells other than the above-described test cells 40, the input cells or input/output cells 50-1 through 50-n having input terminals or input/output terminals. The input/output cells 50-1 through 50-N (N greater than n) shown in FIG. 10 generally refer to output cells having output terminals in addition to input cells or input/output cells having input terminals or input/output terminals. The peripheral circuit region is also provided with power source cells 60-1 through 60-M having power source voltage (VDD) terminals 61 or ground voltage (VSS) terminals 62. FIG. 10 also shows non-connected cells 70-1 through 70-m, which are characteristic for a master slice type semiconductor device. The non-connected cells include input terminals, input/output terminals or output terminals that are not connected to transistors provided in these cells.
The buffer 100 shown in FIG. 9 is disposed in each of the input/output cells 50-1 through 50-N, the power source cells 60-1 through 60-M and the non-connected cells 70-1 through 70-m.
According to the second prior art, even when the wiring capacitance of the control signal wiring 42 is large, the wiring capacitance is divided and distributed to and born by the numerous buffers 100 that are provided in the control signal wiring 42. In other words, the large wiring capacitance of the control signal wiring 42 is divided by the total number of the buffers 100, and born by the buffers 100. Accordingly, the capacity of each of the buffers 100 can be made relatively small. Also, the dependence of the capacitance of the buffer 100 on the chip size is greatly reduced. Moreover, because the numerous buffers 100 are disposed in the control signal wiring 42 and the control signal waveform is rectified by each of the buffers 100, the level of blunting of control signals to be provided to the gates of the N-type and P-type MOS transistors 26, 36 is reduced.
The second prior art technology described above has many more advantages over the first prior art technology. However, since there are a vast number of the buffers 100, a substantially large area is required exclusively for the buffers 100. Also, there occurs another problem in that a control signal is delayed each time it passes each of the numerous buffers 100.
It is therefore an object of the present invention to provide a semiconductor device and a method for manufacturing the same that solves the problems of time delay in turning on and off circuits that fix potentials of signal input wirings and blunting of waveforms, lowers the chip-size dependence of the disposed buffer, and prevent increase in the area occupied by the required circuits.
A semiconductor device in accordance with one embodiment of the present invention includes a peripheral circuit region and a central circuit region in which a plurality of logic circuits are formed. The peripheral circuit region includes at least a first cell having a test terminal, N number of second cells and a plurality of third cells. Each of N number of the second cells is connected to one of a plurality of signal terminals that input and/or output signals. Each of the plurality of third cells has one of power source terminals. Among N number of the second cells, n number of the second cells (n less than N) have input signal wirings in which signals are inputted through the signal terminals, and have potential fixing circuits that fix the potential on the input signal wirings. Each of n number of the potential fixing circuits has a control terminal. The test terminal connects to a control signal wiring that is provided along the peripheral circuit region. The control signal wiring connects to the control terminals of the potential fixing circuits. The control terminals are provided with a logic that turns on the potential fixing circuits during normal operation, to thereby fix the potential of the input signal wirings. When a signal is inputted in the test terminal, the potential fixing circuits turn off. As a result, the input signal wirings are placed in a floating state, and thus the input leak test can be accurately conducted. A plurality of serially connected buffers are provided in the control signal wiring. The plurality of buffers are disposed in a plurality of third cells, but not disposed in the N number of the second cells.
In accordance with one embodiment of the present invention, the third cell having the power source terminal and a power source wiring connected thereto has a larger empty space than that of the second cell having an input circuit, an output circuit or an input/output circuit. As a result, the empty space can be used for placing a buffer. In particular, in a master slice type semiconductor device, pre-formed transistors in the third cells can be used to form buffers, and therefore there is no need to provide extra spaces for buffers.
Moreover, the third cells having the power source terminals are generally evenly distributed along the four edges of the semiconductor device. As a result, an appropriate number of buffers can be distributed in the control signal wiring that is formed along the peripheral circuit region, and thus a load such as the wiring capacitance can be born by the distributed buffers. This arrangement can reduce the capacitance of each buffer. Also, waveform of the control signal is rectified by the distributed buffers. In addition, the number of buffers is substantially reduced compared to the second prior art. As a result, the total amount of control signal delays occurred at the buffers is reduced and thus an input leak test can be performed at a higher speed.
The peripheral circuit region may further include fourth cells that have signal terminals that may not be connected to any internal wirings. The fourth cells of this type are typically present in a master slice type semiconductor device, and generally referred to as non-connected cells. Buffers can be placed in the fourth cells because the fourth cells have relatively large empty spaces which can be utilized for placing buffers. Accordingly, there is no need to provide extra spaces for buffers in the peripheral circuit region.
The peripheral circuit region may have four fifth cells respectively disposed in the four corners thereof. The four fifth cells normally do not have signal terminals or power source terminals. In this case, the four fifth cells provide empty spaces, and a buffer can be disposed in at least one of them.
The drivability of the buffer disposed in the fifth cell may preferably be greater than the drivability of the buffer disposed in the other cells other than the fifth cells.
Because the fifth cells are disposed in the corners, where they can have greater layout areas, the drivability of the buffers can be relatively readily increased. As a result, a buffer capability that is comparable to the buffer capability of the second prior art can be attained without increasing the required area therefor.
The power source terminal may be composed of at least a grounding voltage terminal, a first power source voltage terminal that is supplied with a first power source voltage, and a second power source voltage terminal that is supplied with a second power source voltage lower than the first power source voltage. For example, such an arrangement may be implemented in a semiconductor device that is driven by two different power source voltages, for example 3V and 5V. In this case, buffers may preferably be provided in a third cell having a grounding voltage terminal and in a third cell having a first power source voltage terminal, but a buffer may not be provided in a third cell having a second power source voltage terminal. This is because when an input of 5V is provided to a buffer that is driven by an input of 3V, its maximum output is 3V, which results in troubles.
For example, troubles may occur when at least one of the second cells that is supplied with a first power source voltage inverts the logic of a control signal, and there are provided first CMOS inverters that supply the inverted signal to the potential fixing circuits. In such a case, for example, a voltage of 3V is supplied to each of gates of the CMOS inverters that are driven by a voltage of 5V. As a result, a through current flows in the first CMOS inverters. Therefore, in order to supply 5V (the maximum voltage) to each of the gates of the first CMOS inverters, buffers may preferably be provided in the third cells that have first power source voltage terminals that are supplied with the highest voltage.
With this arrangement, even when at least one of the second cells, that is supplied with a second power source voltage, inverts the logic of the control signal that is provided through the buffer disposed in the third cell that has the first power source voltage terminal, and a second CMOS inverter is provided to supply the inverted signal to the potential fix circuit, a through current does not flow in the second CMOS inverter. However, where the first and second power source voltages are, for example 5V and 3V, respectively, a voltage of 5V from the inverter may be shifted down to 3V, and then supplied to each of the gates of the second CMOS inverters.
In accordance with another embodiment of the present invention, a semiconductor device is manufactured by a method including: the first step of forming a substrate defining a peripheral circuit region and a central circuit region and having a plurality of basic cells, each composed of a predetermined number of transistors; the second step of determining the placement of the cells and wirings therefor to be disposed in the peripheral circuit region and the central circuit region; the third step of routing the plurality of transistors on the substrate based on the determined placement and routing; and the fourth step of cutting the substrate into a plurality of semiconductor devices.
In a preferred embodiment of the present invention, the second step may include a plurality of steps. One of the steps includes determining the placement of a first cell having a test terminal, N number of second cells for inputting and/or outputting signals, each connected to a signal terminal, a plurality of third cells, each having a power source terminal, and fourth cells, each having a signal terminal that is not connected to any internal wiring.
Another one of the steps includes disposing, among N number of the second cells, voltage fixing circuits in n (n less than N) number of the second cells that have input signal wirings to which signals are inputed through the signal terminals for fixing potentials of the signal input wirings.
Still another one of the steps includes disposing, in the third and fourth cells, buffers to be connected to the control signal wiring that connects to the test terminal and extends along the peripheral circuit region.
In accordance with another embodiment of the present invention, semiconductor devices in accordance with one of the above-described embodiments are manufactured from a master slice.
In the case of a master slice, the second step may preferably include disposing a buffer in at least one of four fifth cells that are disposed in the four corners of the peripheral circuit region. In this case, in the first step, the drivability of transistors disposed in the fifth cells may preferably be greater than the drivability of the transistors disposed in the first through fourth cells.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.